1. Field of the Invention
This invention relates to a semiconductor integrated circuit device such as a synchronous RAM (Random Access Memory) and a pipeline RAM.
2. Description of the Related Art
As the operation speed of microcomputers, etc., has become higher and higher in recent years, a higher operation speed has been required for peripheral devices such as a memory, and high speed devices such as a synchronous RAM, a pipeline RAM, etc., have been used.
FIG. 6 of the accompanying drawings is a conceptual block diagram of a pipeline RAM according to the prior art. This pipeline RAM includes a first pipeline stage for inputting an input signal (which is an address signal) into an input buffer 1, a second pipeline stage for decoding the input signal by row/column decoders 2, a third pipeline stage for latching data read out from a memory cell array 3 (the output of a sense amplifier 4) in accordance with the decoding result, and a fourth pipeline stage for outputting the latch data through an output buffer 5. This pipeline RAM can accomplish a high speed operation in accordance with the number of pipeline stages by the parallel operations of the first to fourth pipeline stages.
Here, the operation of each pipeline stage is determined by first to fourth internal clocks CLKIN #1 to #4, and these internal clock signals CLKIN #1 to #4 are generated by each block 6a to 6d (inclusive of an input buffer and a clock generation portion) of a signal generation circuit 6 on the basis of an external clock signal CLKEX.
However, the semiconductor integrated circuit device according to the prior art described above involves the problem that when the frequency of the input signal DIN or that of the external clock signal CLKEX is increased, matching cannot be established between the data at each pipeline stage and the external clock. Therefore the circuit operates erroneously, and this is a problem which must definitely be solved in order to further improve operation speed.
FIG. 7 is a timing chart of the internal clock signal CLKIN #1 that determines the operation of the first pipeline stage and the input signal DIN of this stage, for example. In this timing chart, the shift timing of the internal clock signal CLKIN #1 (the rise shift timing for the sake of convenience) exists within a definite period of the input signal DIN. Therefore, the signal can be input without any problem. However, when the frequency of the input signal DIN is increased, the definite period described above becomes shorter, so that the shift timing of the internal clock signal CLKIN #1 is likely to stray from the definite period T or is likely to enter the definite period of a next input signal.